ND Show HN: ML accelerator on a RISC-V FPGA SoC – zero-cycle matmul, boots Linux (dstrbad.substack.com)
2 points by dstrbad 10 days ago | 0 comments on HN ~lite vlite-2.0
Summary ~lite
Technical article on building an ML accelerator from scratch on an FPGA.
Lite evaluation by llama-4-scout-wai-psq · editorial channel only · no per-section breakdown available
Longitudinal 32 HN snapshots · 2 evals
+1 0 −1 HN
Audit Trail 5 entries
2026-03-21 00:58 eval_success PSQ evaluated: g-PSQ=0.280 (3 dims) - -
2026-03-21 00:58 eval Evaluated by llama-4-scout-wai-psq: +0.28 (Mild positive)
2026-03-21 00:53 eval_success Lite evaluated: Neutral (0.00) - -
2026-03-21 00:53 rater_validation_warn Lite validation warnings for model llama-4-scout-wai: 1W 0R - -
2026-03-21 00:53 eval Evaluated by llama-4-scout-wai: 0.00 (Neutral)
reasoning
Technical article on building an ML accelerator, no explicit human rights discussion